1. Field of the Invention
The present invention relates to a semiconductor memory device with an improved memory cell structure and a method of operating the same, and more particularly to a random access memory device with an improved memory cell structure, wherein each memory cell includes a pair of a non-volatile memory element and a volatile memory element, and a method of operating the semiconductor memory device.
All of patents, patent applications, patent publications, scientific articles and the like, which will hereinafter be cited or identified in the present application, will, hereby, be incorporated by references in their entirety in order to describe more fully the state of the art, to which the present invention pertains.
2. Description of the Related Art
In general, the DRAM cell is one of the lowest-cost memory cells. The DRAM cell is suitable for high speed performance, but is volatile and allows stored data to disappear upon power-off. Due to this volatility, the DRAM cell is unlikely to be used for a variety of mobile devices which need a reduced or lower power consumption. Another semiconductor device has been proposed, which both exhibits such a high speed performance as DRAM and takes such a reduced power consumption as non-volatile memories such as Flash memories. Instead of the volatile semiconductor memory cell typically the DRAM cell, one of the non-volatile semiconductor memory devices, for example a FRAM has already been known, which has a cell structure generally similar to the DRAM memory cell, except that a capacitor of the memory cell comprises a non-volatile material.
One of the conventional non-volatile semiconductor memory devices is disclosed in Japanese laid-open patent publication No. 11-126492. FIG. 1 is a circuit diagram illustrative of this conventional non-volatile semiconductor memory device. The non-volatile semiconductor memory device includes a memory cell array 1, a pre-charge circuit 2 connected to the memory cell array 1, a bit line selector 3 connected to the pre-charge circuit 2, a voltage adjusting circuit 4 connected to the bit line selector 3, and sense amplifiers SA connected to the voltage adjusting circuit 4.
The memory cell array 1 further includes a memory cell area 10 and a register area 11′ which is positioned between the memory cell area 10 and the pre-charge circuit 2. The memory cell area 10 furthermore includes a plurality of memory cells Mo0 . . . Mom−1. Each of the memory cells Mo0 . . . Mom−1 includes a pair of a flash cell and a DRAM capacitor. The flash cell comprises a non-volatile transistor. The DRAM capacitor comprises a capacitor included in the normal DRAM cell. A drain of the non-volatile transistor serving as the flash cell is connected to a bit line BL. A source of the non-volatile transistor serving as the flash cell is connected to a first terminal of the DRAM capacitor. A second terminal of the DRAM capacitor is connected to a power terminal VPL.
The above conventional non-volatile semiconductor memory device operates in both a normal operation mode and a data holding mode. In the normal operation mode, data are stored in the DRAM capacitor, and the stored data are read out from the DRAM capacitor. In this normal operation mode, a high speed random access to the memory cell is obtained as in the normal DRAM cell. In the data holding mode, data are stored in the flash cell or the non-volatile transistor.
In the data holding mode, the flash cell serves as a non-volatile memory. In the normal operation mode, the flash cell serves as a switching transistor of the normal DRAM cell, wherein data are transmitted from a bit line through the flash cell to the DRAM capacitor, wherein the data are stored in the DRAM capacitor. The data stored in the DRAM capacitor are read out through the flash cell.
The non-volatile transistor constituting the flash cell not only serves as a non-volatile memory in the data holding mode, but also serves as a selective switching element whenever data read/write operations are made. Namely every time data are read or write, a word line is activated which is connected to a gate electrode of the non-volatile transistor, so that the non-volatile transistor turns ON. The above two operations as the switching element and the non-volatile memory element in both the normal operation mode and the data holding mode means that the non-volatile transistor is needed to perform an increased number of ON/OFF operations at a high ON/OFF switching speed, as compared to the normal case that the non-volatile transistor is simply operated as a non-volatile memory in the data holding mode only.
The non-volatile transistor constituting the flash cell is generally inferior in the high speed performance such as the ON-OFF switching operation and its cyclic characteristic or durability as compared to the normal switching transistor used in the DRAM cell. It is necessary for the non-volatile transistor to improve a cyclic characteristic or a durability of a gate insulation film material of the non-volatile transistor, and also improve a stability in performance of the non-volatile transistor. Even if an ideal gate insulating film with a superior film quality could be developed, then this may cause an increase in the cost of the non-volatile transistor.
Another example of the conventional non-volatile semiconductor memory devices is disclosed in Japanese laid-open patent publication No. 7-78484. FIG. 2 is an equivalent circuit diagram illustrative of a memory cell included in this conventional non-volatile semiconductor memory device. The memory cell comprises a selecting transistor Tr, and plural pairs of a capacitor Co comprising a parasitic capacitance, and a floating gate non-volatile memory transistor M. A drain of the floating gate non-volatile memory transistor M is connected through a sub-bit line SBL and a single selecting transistor Tr to a main bit line MBL. The sub-bit line SBL is connected through the selecting transistor Tr to the main bit line MBL. A source of the floating gate non-volatile memory transistor M is connected to a ground line GND.
It may equivalently be considered that each of the plural floating gate non-volatile memory transistors M has a parasitic capacitance Co connected to the source of the selecting transistor Tr in parallel to each of the plural floating gate non-volatile memory transistors M.
Illustration being omitted, in each memory cell, plural pairs of the floating gate non-volatile memory transistors M1 –Mn and the parasitic capacitances C1–Cn are connected in parallel to each other through the single selecting transistor Tr to the main bit line MBL. Assuming that a parasitic capacitance Co* corresponds to a total sum of the parasitic capacitances C1–Cn, it may equivalently be considered that the parasitic capacitance Co* is connected through the selecting transistor Tr to the main bit line MBL.
In other words, it may also equivalently be considered that each of the memory cells comprises a non-volatile memory transistor Mk and a DRAM cell structure, wherein the non-volatile memory transistor Mk further comprises a plurality of the floating gate non-volatile memory transistors M1–Mn which are connected in parallel to each other to the source of the selecting transistor Tr, while the DRAM cell structure comprises a single selecting transistor Tr and the parasitic capacitance Co* corresponds to the total sum of the plural parasitic capacitances C1–Cn respectively provided by the plural floating gate non-volatile memory transistors M1–Mn.
This non-volatile memory transistor not only stores data in the data holding mode but also operates as the normal capacitive element in the normal DRAM cell for read and write operations in the normal operation mode. Every time of the data read and write operations, there rises a word line connected to a gate electrode of the non-volatile memory transistor Mk for causing the non-volatile memory transistor Mk to turn ON. The operations in the normal operation mode include a large number of ON/OFF switching operations of the transistor and need the high speed ON/OFF switching operations of the transistor as compared to the other operations as memory transistor in the data holding mode.
It is the fact that the non-volatile memory transistor is in general inferior in the high speed performance and cyclic characteristic of the ON/OFF switching operations, as compared to the selecting transistor used in the normal DRAM cell. For this reason, it is necessary for the non-volatile memory transistor to improve a cyclic characteristic or a durability of a gate insulation film material of the non-volatile memory transistor, and also improve a stability in performance of the non-volatile memory transistor. Even if an ideal gate insulating film with a superior film quality could be developed, then this may cause an increase in the cost of the non-volatile memory transistor.
In accordance with the above-described conventional techniques, the non-volatile transistor not only serves as the non-volatile memory in the data holding mode, but also serves as the selective switching element whenever data read/write operations are made. Therefore, it is necessary for the non-volatile memory transistor to improve a cyclic characteristic or a durability of a gate insulation film material of the non-volatile memory transistor, and also improve a stability in performance of the non-volatile memory transistor. Even if an ideal gate insulating film with a superior film quality could be developed, then this may cause an increase in the cost of the non-volatile memory transistor.
In the above circumstances, there is desired the development of a novel semiconductor memory device and a method of controlling the same, free from the above problems.